A common method of testing memory devices is to place several memory devices within a single die and use multiplexers to route signals on and off the chip to cut down on the number of pads required to read the test results. Due to the large number of memory devices being tested, it proves difficult to route the signals on and off the chip such that signal skew between them does not occur. This limits the amount of characterization information which can be gathered from the test chip. For example, the large skews between the signals at the memory render any setup/hold timing information obtained essentially useless. Additionally, the delay relating to routing the signals on and off the chip inhibits the gathering of access timing information.